Generally, for designing a relaxation oscillator of an integrated circuit, it is necessary to perform a clock trimming action. After the clock trimming action is done, the relaxation oscillator may generate the accurate clock signals.
For example, a system for reducing the test time of an internal oscillator has been disclosed in U.S. Pat. No. 8,058,893, which is entitled “Frequency trimming for internal oscillator for test-time reduction”. FIG. 1A schematically illustrates the architecture of a conventional clock trimming system. FIG. 1B is a schematic timing waveform diagram illustrating associated signals processed by the conventional clock trimming system of FIG. 1A. The conventional clock trimming system 10 is disclosed in U.S. Pat. No. 8,058,893, and comprises a tester 12 and a microcontroller integrated circuit 11. The microcontroller integrated circuit 11 comprises a crystal oscillator 21, an on-chip oscillator 13, a bus 19, a memory 18, a trimming register 15, a processor 17, an on-chip debugger 22, an I/O register 16, a timer 14, a multiplexer (MUX) 20, and plural terminals 23˜26.
After the system 10 starts to perform a clock trimming action, a test program 28 in the tester 12 is firstly converted into a serial data. Then, the serial data is transmitted to and stored into the memory 18 through the terminal 26, the on-chip debugger 22 and the bus 19. Then, according to the test program 28, the processor 17 generates a trimming value to the trimming register 15 and provides a control signal Control with a logic state “1” to the multiplexer 20. According to the trimming value in the trimming register 15, the on-chip oscillator 13 generates a clock signal CLK to the timer 14 through the multiplexer 20.
In case that a reference signal in a high-level state is outputted from the tester 12 to the timer 14 through the terminal 23, the timer 14 is enabled to start to count the pulse number of the clock signal CLK. When the reference signal goes to the low level, a counting value Count is outputted from the timer 14 to the processor 17 through the bus 19. Moreover, according to the counting value Count, the trimming value 29 is adjusted by the processor 17. Consequently, the frequency trimming action of the clock signal CLK is done.
The above steps are repeatedly performed. That is, the processor 17 will sequentially generate different trimming values and judge the clock signal CLK according to the counting value Count from the timer 14. In case that the counting value Count received by the processor 17 complies with a predetermined value, it is determined that the frequency of the clock signal CLK reaches a predetermined frequency. Meanwhile, the corresponding trimming value 29 is stored into the memory 18. Afterwards, the processor 17 controls the I/O register 16 to issue a completion signal Done to the tester 12 through the terminal 24. The completion signal Done may inform the tester 12 that the clock trimming action is completed. On the other hand, after the trimming values are sequentially generated by the processor 17, if the corresponding counting values Count fail to comply with the predetermined value, the processor 17 controls the I/O register 16 to issue a fail signal Fail to the tester 12 through the terminal 25. The fail signal Fail may inform the tester 12 that the clock trimming action is failed.
Please refer to FIG. 1B. It is assumed that the system 10 intends to adjust the frequency of the clock signal CLK to a target oscillation frequency of 1000 Hz. If the counting value generated by the timer 14 is 7 during the high-level time period (10 milliseconds) of the reference signal, the clock signal CLK generated by the on-chip oscillator 13 has a slower oscillation frequency of about 700 Hz. In other words, the on-chip oscillator 13 may be considered as a slow oscillator. Under this circumstance, the trimming value needs to be increased by the processor 17.
On the other hand, if the counting value generated by the timer 14 is 13 during the high-level time period (10 milliseconds) of the reference signal, the clock signal CLK generated by the on-chip oscillator 13 has a faster oscillation frequency of about 1300 Hz. In other words, the on-chip oscillator 13 may be considered as a fast oscillator. Under this circumstance, the trimming value needs to be decreased by the processor 17.
On the other hand, if the counting value generated by the timer 14 is 10 during the high-level time period (10 milliseconds) of the reference signal, the clock signal CLK generated by the on-chip oscillator 13 has an accurate oscillation frequency of about 1000 Hz. In other words, the on-chip oscillator 13 may be considered as an accurate oscillator. Under this circumstance, the corresponding trimming value is recorded into the memory 18 by the processor 17, and the clock trimming action is completed.
However, as mentioned in U.S. Pat. No. 8,058,893, some drawbacks may occur. For example, since the reference signal and clock signal CLK are not synchronized, the measuring error (Δt) may be miscounted by up to one cycle.